(a) Field of the Invention
The present invention relates to a comparator and a control circuit for controlling a power MOSFET (metal-oxide-semiconductor field effect transistor).
(b) Description of the Related Art
Power MOSFETs are used in a variety of applications in a power supply circuit. FIG. 1 is a circuit diagram showing a conventional control circuit for controlling a power MOSFET.
The control circuit includes an N-channel depletion FET MD10, N-channel enhancement FETs ME 10 and ME 11, high-resistance resistors R 10 to 12 made of polycrystalline silicon films, and a power MOSFET PoMOSFET.
In FIG. 1, the control circuit includes first through third serial branches. The first serial branch has the high-resistance resistors R11 and R12 of polycrystalline silicon films, connected in series between the input terminal IN and the ground terminal GND. The second serial branch has the N-channel depletion FET MD10 and the N-channel enhancement FET ME10 connected in series between the input terminal IN and the ground terminal GND. The third serial branch has the high-resistance resistor R12 of polycrystalline silicon film and the N-channel enhancement FET ME11 connected in series between the input terminal IN and the ground GND.
In addition, the node connecting the resistors R10 and R11 is connected to the gate of the N-channel enhancement FET ME10. The connection node of the high-resistance resistor R12 and the drain terminal of the N-channel enhancement FET ME11 is connected to the gate terminal of the power MOSFET. In addition, the gate terminal of the N-channel enhancement FET ME11 is connected to the drain terminal of the N-channel enhancement FET ME10.
In the control circuit arranged as described above, the first serial branch acts as an input voltage divider circuit, the second serial branch acts as a reference voltage circuit, and the third serial branch acts as an inverter circuit. The output terminal OUT or the drain of the power MOSFET is connected to a load not shown.
In FIG. 1, the voltage V10 is obtained by dividing the input voltage VIN by using the high-resistance resistors R10 and R11 and is changed in accordance with the level of the input voltage VIN. Thus, the following equation holds:
V10={R11/(R10+R11)}xc2x7VIN.
A variation in the voltage V10 is compared against the threshold voltage Vt of the N-channel enhancement FET ME10. If the input voltage VIN is lower compared to a specified voltage, an output voltage Vg2 of the inverter circuit assumes a low level since V10 less than Vt of ME10 holds. On the other hand, if the input voltage VIN is higher compared to the specified voltage, the output voltage Vg2 of the inverter circuit assumes a high level since V10 greater than Vt of ME10 holds. In this case, the high voltage Vg2 applied to the gate terminal of the power MOSFET turns on the power MOSFET to flow a current through the load.
FIG. 2 is a graph showing the voltage characteristic of each portion of the control circuit of FIG. 1 against the input voltage VIN during performing the gate control of the power MOSFET based on the input voltage VIN. It is to be noted that the N-channel enhancement FET ME10 has a threshold voltage Vt of about 0.6V, whereas the power MOSFET has a threshold voltage Vtp of about 1.2V. In FIG. 3, if the resistor R10 has a resistance of 300 kxcexa9 and the resistor R11 has a resistance of 140 kxcexa9, with the input voltage VIN being at about 2V, the node V10 has a voltage of about 0.6V to turn on the N-channel enhancement FET ME10. In this case, the gate voltage Vg2 of the power MOSFET assumes a high level.
As described above, in the conventional control circuit having a comparator function therein, the threshold voltage Vt of the N-channel enhancement FET ME10 is employed as a reference voltage, which is compared against the voltage V10 obtained by dividing the input voltage VIN with the high-resistance resistors R10 and R11 of polycrystalline silicon films to perform the gate control of the power MOSFET.
In the conventional control circuit, however, there was a drawback in that the control voltage for controlling ON/OFF of the power MOSFET is varied depending on the variation of the threshold voltage Vt of the N-channel enhancement FET.
For example, in FIG. 2, with a variation in the threshold voltage Vt of the N-channel enhancement FET ME10 being within a range of xc2x10.2V, the control voltage VTH for controlling ON/OFF of the power MOSFET significantly varies within a range of about xc2x10.5V, as shown in FIG. 2. Taking also the variation of the ON-current of the N-channel depletion FET MD10 into consideration, the control voltage VTH for controlling the ON/OFF of the power MOSFET varies in a higher range of xc2x11.0V or more.
It is therefore an object of the present invention to solve the aforementioned conventional drawback to provide a control circuit having a reduced variation in the control voltage for controlling ON/OFF of the power MOSFET by using a new configuration of a comparator. The present invention also relates to such a comparator.
The present invention provides a comparator comprising:
a differential pair including a pair of depletion transistors each having a gate for receiving one of a signal pair; and
a current mirror including a pair of enhancement transistors each connected in series with a corresponding one of the depletion transistors, a drain of one of the enhancement transistors forming an output terminal for outputting a result of comparison between the signal pair by the comparator.
In accordance with the control circuit of the present invention having a new comparator, variations in the control voltage for ON/OFF control can be reduced.
The present invention also provides a control circuit comprising:
a voltage divider for diving an input voltage to input a divided voltage;
a fixed voltage generator for generating a fixed voltage:
a differential pair including first and second depletion transistors, the first depletion transistor having a gate for receiving the divided voltage, the second depletion transistor having a gate for receiving the fixed voltage,
a current mirror including first and second enhancement transistors, the first enhancement transistor being connected in series with the first depletion transistor, the second enhancement transistor being connected in series with the second depletion transistor, a drain of one of the first and second enhancement transistors outputting a result signal indicating a result of comparison between the fixed voltage and the divided voltage; and
a first MOSFET having a gate controlled by the result signal.
In accordance with the control circuit of the present invention having a new comparator, a variation in the control voltage for ON/OFF control can be reduced by the function of the comparator having a new configuration.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.